Cover of S. Jayanthy, M.C. Bhuvaneswari: Test Generation of Crosstalk Delay Faults in VLSI Circuits

S. Jayanthy, M.C. Bhuvaneswari Test Generation of Crosstalk Delay Faults in VLSI Circuits

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Springer Nature Singapore

2018

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978-981-1324-93-2

981-1324-93-X

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This book describes a variety of test generation algorithms for testing crosstalk delay faults in VLSI circuits. It introduces readers to the various crosstalk effects and describes both deterministic and simulation-based methods for testing crosstalk delay faults. The book begins with a focus on currently available crosstalk delay models, test generation algorithms for delay faults and crosstalk delay faults, before moving on to deterministic algorithms and simulation-based algorithms used to test crosstalk delay faults. Given its depth of coverage, the book will be of interest to design engineers and researchers in the field of VLSI Testing.

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